Information Technology
More Efficient, Portable Graphic Processing System by Exception Handling
WARF: P120164US01
Inventors: Karthikeyan Sankaralingam, Jaikrishnan Menon, Marc De Kruijf
The Wisconsin Alumni Research Foundation (WARF) is seeking commercial partners interested in developing a method for modifying hardware to provide exception handling by graphic processing units without the need for extensive storage capacity for recording architectural state.
Overview
‘Exceptions’ are occurrences during the execution of a computer program that interrupt the normal program flow dictated by the instructions themselves. These include non-valid instructions, like division by zero, and page faults—occurring when a memory resource is unavailable.
An exception normally is handled by a special circuit of the processor that detects it and responds by saving the state of the processor (e.g., processor registers) and jumping to a ‘handler,’ or subroutine written to treat a specific exception.
Exception handling can be a challenge for graphic processing units (GPUs), in which a large number of elements operate to perform graphic tasks like shading, rotation and other geometric manipulations. Handling is difficult because of the complex architectural state of the processor, which would require saving and storing hundreds and thousands of registers. Simplifying the system could dramatically improve processor efficiency.
An exception normally is handled by a special circuit of the processor that detects it and responds by saving the state of the processor (e.g., processor registers) and jumping to a ‘handler,’ or subroutine written to treat a specific exception.
Exception handling can be a challenge for graphic processing units (GPUs), in which a large number of elements operate to perform graphic tasks like shading, rotation and other geometric manipulations. Handling is difficult because of the complex architectural state of the processor, which would require saving and storing hundreds and thousands of registers. Simplifying the system could dramatically improve processor efficiency.
The Invention
UW–Madison researchers have developed a method for GPU exception handling that overcomes the problem of state storage by identifying idempotent regions of the executed code. Idempotence describes an operation that produces the same results if executed once or multiple times, meaning it can be retried as often as necessary without causing unintended effects. Identifying these regions allows a state to be restored (without storage) by simply moving backward in the program.
The method decomposes GPU programs into idempotent sequences and regions. GPU programs tend to have very large regions of code that are idempotent. They can be used to rapidly service infrequent exceptions and those, like page faults, that require a context switch. For data mis-speculations, regions can be further divided into fast idempotent sub-regions. Additionally, a compiler incorporated into the GPU architecture reviews instructions to identify idempotent regions and mark those readable by the GPU.
The method decomposes GPU programs into idempotent sequences and regions. GPU programs tend to have very large regions of code that are idempotent. They can be used to rapidly service infrequent exceptions and those, like page faults, that require a context switch. For data mis-speculations, regions can be further divided into fast idempotent sub-regions. Additionally, a compiler incorporated into the GPU architecture reviews instructions to identify idempotent regions and mark those readable by the GPU.
Applications
- Design and manufacture of GPUs
- Incorporation into computers, smartphones, gaming consoles and other devices
Key Benefits
- Technique can be supported by small hardware modification and is widely applicable to different types of exceptions.
- Requires little additional overhead and leverages the benefits of idempotence
- Provides handling for processor units where state storage is difficult
- Ensures program goes forward from the exception correctly
- Uses simple mechanism applicable to a wide variety of architectures
Additional Information
For More Information About the Inventors
Related Intellectual Property
Publications
- Menon J., De Kruijf M. and Sankaralingam K. 2012. iGPU: Exception Support and Speculative Execution on GPUs. ISCA [39th International Symposium on Computer Architecture]
Tech Fields
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