Information Technology
LEAP - Improved Data Lookup for High-Speed Routers
WARF: P120239US01
Inventors: Karthikeyan Sankaralingam, Eric Harris, Samuel Wasmundt
The Wisconsin Alumni Research Foundation (WARF) is seeking commercial partners interested in developing a packet processing engine using a tile-based architecture that is efficient and flexible.
Overview
Networks allow data exchange between linked computers. Data messages are divided into packets, which are able to navigate complex and changing networks. A router, or switch, reads packet addresses and steers them through the links to a destination.
All the functions of a router require it to look up packet addresses in memory, and to perform rapidly and repeatedly. The effectiveness of a router is largely a function of how quickly memory lookups can be completed. High-performance routers may use a type of whole-memory searching to save time, but this involves more power and heat.
Current methods of packet processing are unlikely to meet the needs of increasingly complicated networks.
All the functions of a router require it to look up packet addresses in memory, and to perform rapidly and repeatedly. The effectiveness of a router is largely a function of how quickly memory lookups can be completed. High-performance routers may use a type of whole-memory searching to save time, but this involves more power and heat.
Current methods of packet processing are unlikely to meet the needs of increasingly complicated networks.
The Invention
UW–Madison researchers have developed LEAP (Latency, Energy and Area Optimized Lookup Pipeline), an improved tile-based approach for routing data packets in a network.
The router has a series of ports for receiving and transmitting packets, and communicating with a general-purpose processor. The router’s packet processing engine receives data and conducts memory lookups. The engine includes a set of connected computational tiles. Each tile has a set of functional units with inputs and outputs for processing arguments, and a store for holding instructions. Also, the tiles have a programmable multiway switch for communicating with the functional units and act according to the stored instructions.
The functional units may access a lookup memory holding packet data while interconnection circuitry manages communication of data between tiles.
The router has a series of ports for receiving and transmitting packets, and communicating with a general-purpose processor. The router’s packet processing engine receives data and conducts memory lookups. The engine includes a set of connected computational tiles. Each tile has a set of functional units with inputs and outputs for processing arguments, and a store for holding instructions. Also, the tiles have a programmable multiway switch for communicating with the functional units and act according to the stored instructions.
The functional units may access a lookup memory holding packet data while interconnection circuitry manages communication of data between tiles.
Applications
- High-speed network routing
Key Benefits
- Router merges performance and flexibility.
- Simple hardware elements produce sophisticated lookup functions.
- Ready implementation
- Low latency processing with extremely fast functional units
- Versatile
- Provides programmability and a variety of high-speed functions
Additional Information
For More Information About the Inventors
Related Technologies
Tech Fields
For current licensing status, please contact Jeanine Burmania at [javascript protected email address] or 608-960-9846